PXB4219E Datasheet, PDF (25/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

2.2.2 UTOPIA Interface
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
Table 2
Pin No.
U12, V12,
W12, Y12,
U11, V11,
W11, Y11
Y13
W10
V10
V13
W13
UTOPIA Interface (36 pins)
Symbol
Input (I) Function
Output (O)
RXDAT[7:0] O
PUA
UTOPIA Receive Data Bus
Byte-wide data driven from PHY to ATM
layer. RxData[7] is the MSB.
RXPTY
RXSOC
RXCLAV
RXCLK
RXENB
O
PUA
O
PDA
Slave: O
Master: I
PDA
I
Slave: I
Master: O
PUA
UTOPIA Receive Odd Parity Bit
Odd parity for RXDAT[0:7] driven by the
PHY layer.
UTOPIA Receive Start-of-Cell
Active high signal asserted by the PHY layer
when RXDAT[0:7] contains the first valid
byte of a cell.
UTOPIA Receive Cell Available
Slave: RXCLAV is an active high signal
asserted by the PHY layer to indicate that it
has data available for transfer to the ATM
layer.
Master: RXCLAV is an active high signal
asserted by the ATM layer to indicate that it
has data available for transfer to the PHY
layer.
UTOPIA Receive Clock
Transfer/synchronization clock from the
ATM layer to the PHY layer for
synchronizing transfers on RXDAT[0:7].
UTOPIA Receive Enable
Slave: Active low signal asserted by the
ATM layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
Master: Active low signal asserted by the
PHY layer to indicate that RXDAT[0:7] and
RXSOC will be sampled at the end of the
next cycle.
Data Sheet
25
2003-01-20