PXB4219E Datasheet, PDF (141/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 1 port_nr
[2:0]
channel_nr
[4:0]
counter_nr 0
[3:0]
The format of the counter threshold entries is as follows:
31
thres_act
23
15
7
24
thres_value[30:24]
16
thres_value[23:16]
8
thres_value[15:8]
0
thres_value[7:0]
thres_act
thres_value
threshold active
0 = Disabled
1 = Enabled
threshold value
Thresholds beyond 4000 0000_H will never create an interrupt queue
entry as the counter stops at this value
6.2.3 Interrupt Queue
Read/write Address 24000_H to 25FFF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size: 4K × 32 bits
RMADR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
10010
interrupt_queue_addr[11:0]
0
Data Sheet
141
2003-01-20