PXB4219E Datasheet, PDF (259/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Electrical Characteristics
Table 44 Transmit Timing (8-Bit Data Bus, 33 MHz, Multi-PHY)
No. Signal Name DIR Description
Limit Values
Min
Max
t1 TXCLK¹⁾
A>P TXCLK frequency (nominal) 0
33
tT2
TXCLK duty cycle
40
60
tT3
TXCLK peak-to-peak jitter -
5
tT4
TXCLK rise/fall time
-
3
tT5 TXDAT[7:0], A>P Input setup to TXCLK
8
-
tT6 ^TXPTY,
TXSOC,
Input hold from TXCLK
1
-
TXENB,
TXADR[4:0]
tT7 TXCLAV
A<P Input setup to TXCLK
8
-
tT8
Input hold from TXCLK
1
-
tT9
Signal going low impedance 8
-
to TXCLK
tT10
Signal going high impedance 0
-
to TXCLK
tT11
Signal going low impedance 1
-
from TXCLK
tT12
Signal going high impedance 1
-
from TXCLK
1) _{The frequency should be equal or smaller than the coreclock CLOCK}
Unit
MHz
%
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 45 Receive Timing (8-Bit Data Bus, 33 MHz, Multi-PHY)
No. Signal Name DIR Description
Limit Values
Min
Max
t1 RXCLK¹⁾
A>P RXCLK frequency (nominal) 0
33
tT2
RXCLK duty cycle
40
60
tT3
RXCLK peak-to-peak jitter -
5
tT4
RXCLK rise/fall time
-
3
tT5 RXENB,
A>P Input setup to RXCLK
8
-
tT6 ^RXADR[4:0]
Input hold from RXCLK
1
-
Unit
MHz
%
%
ns
ns
ns
Data Sheet
259
2003-01-20