PXB4219E Datasheet, PDF (164/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Register Description
7.11
Loopback Control Register (lpbc)
Read/write Address 00011_H
Reset value: 0000_H
15
8
Not used
tslp
7
0
tulp
tdlp vci_flt_
ulp
vci_val_ulp[4:0]
t
tslp
tulp
tdlp
vci_flt_ulp
vci_val_ulp
Transparent serial loop
0 = Non-transparent
1 = Transparent
Transparent upstream UTOPIA loop
X = When pcfN[p_atm] = 1
0 = Non-transparent
1 = Transparent
Transparent downstream UTOPIA loop
0 = Non-transparent
1 = Transparent
VCI filter enable for upstream UTOPIA loop
0 = Disabled (all VCIs are looped)
1 = Enabled (VCI selected by vci_val_ulp is looped)
5 LSB of the VCI value (i.e. channel number) to be looped on upstream
UTOPIA loop
Note: Transparent loop: Data is looped and forwarded.
Non-transparent loop: Data is looped.
Note: For ATM ports with upstream UTOPIA loopback (pcfN[p_atm] = 1 and
pcfN[p_ulp] = 1), all cells are looped regardless of their VCI value. The vci_flt_ulp
and vci_val_ulp[4:0] bits are don’t care.
Data Sheet
164
2003-01-20