PXB4219E Datasheet, PDF (121/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
6.1.1 RAM1: Receive Port Configuration
Read/write Address 00200_H to 003FF_H
Reset value: Not applicable. RAM must be reset and initialized via SW
Memory size 256K × 32 bits: 8 ports x 32 slots x 1 doubleword
MPADR 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 port_nr
[2:0]
slot[4:0]
6.1.1.1 RAM1: ATM Receive Reference Slot
Read/write Address 00200_H to 003FF_H
Reset value: Not applicable. RAM must be reset and initialized via SW.
31
23
15
7
ocd_start ocd_end
_intrpt _intrpt
Not used
Not used
Not used
go_hunt delete_ x43_ channel_mode[1:0]
idle_cells descram
bling
24
16
8
0
ref_slot
=1
ocd_start_
intrpt
ocd_end_
intrpt
go_hunt
Generate interrupt when OCD state starts
0 = Disabled
1 = Enabled
Generate interrupt when OCD state ends
0 = Disabled
1 = Enabled
Go to hunt state
Data Sheet
121
2003-01-20