PXB4219E Datasheet, PDF (27/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

Table 2
Pin No.
U7
W4, Y2,
W3, Y1,
W2
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
UTOPIA Interface (36 pins) (cont’d)
Symbol
Input (I) Function
Output (O)
TXENB
Slave: I
Master: O
PUA
UTOPIA Transmit Enable
Slave: Active low signal asserted by the
ATM layer during cycles when
TXDAT[0:7] contains valid cell data.
Master: Active low signal asserted by
the PHY layer during cycles when
TXDAT[0:7] contains valid cell data.
TXADR[4:0] I
PUA
UTOPIA Transmit Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to poll and select the
appropriate MPHY device. TXADR4 is the
MSB.
2.2.3 IMA Interface
Table 3
Pin No.
Y10
L20
Y5, W5,
M1
IMA Interface
Symbol
Input (I) Function
Output (O)
ATBTC
O
Tri
ATM Transmit Buffer Threshold
Crossing
Indicates if the difference between the write
and read pointer of the mapping buffer
became smaller than a SW selectable
threshold
UNCHEC
O
Tri
Uncorrectable HEC Error
Indicates if a cell has been discarded due to
an uncorrectable HEC error
PN[2:0]
O
Tri
Port Number
Indicates the port number where the cell
causing ATBT or UNCHEC being asserted
came from
Data Sheet
27
2003-01-20