PXB4219E Datasheet, PDF (112/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
5.5
Microprocessor Interface
IWE8 contains internal registers, 4 internal RAMs and an external RAM that can be read
and written via the Microprocessor Interface.
As access to the internal registers is 16-bit oriented, the Microprocessor Address Bus
(MPADR) is designed for 16-bit boundaries. Access to the 32-bit-wide internal or
external RAM has to be executed in two consecutive 16 bit cycles.
The Microprocessor data bus (MPDAT) has “little endian” word order. Little to big endian
conversion may be implemented either by initialization of the microcontroller or by
hardwiring MPDAT[7:0] to DATA[15:8] and MPDAT[15:8] to DATA[7:0] respectively,
The 32 bit oriented accesses have to be done by two consecutive 16 bit accesses, the
first with MPADR[0] = 0 and the second with MPADR[0] = 1. The IWE8 will not verify
whether the address bits MPADR[17:1] during the second access are the same as
during the first access.
The data of the first of two consecutive write cycles (MPADR[0] = 0) is written temporarily
into an internal write-cache register. The second write cycle (MPADR[0] = 1) causes the
data to be written into internal or external RAM. Bits [15:0] are written from the internal
write-cache register and bits [31:16] are transferred from MPDAT
During the first of two consecutive read cycles (MPADR[0] = 0), the 32 bit data are
actually read from internal or external RAM. Bits [15:0] are transferred to the databus
MPDAT. Bits [31:16] are written into an internal read-cache register. During the second
read (MPADR[0] = 1) the read-cache register is transferred to the databus. When only
bits [15:0] are needed, the second read cycle can be omitted.
For proper operation without acknowledge handshake via MPRDY 23 waitstates can be
used.
5.5.1 Interrupt Handling
The IWE8 provides two independent interrupt pins MPIR1 and MPIR2. The interrupt
handling software should read the interrupt status registers to identify the causes of the
interrupt.
MPIR1 is the main interrupt pin indicating a special event in the IWE8. The interrupt
cause can be determined by reading Interrupt Status Register 1 ("isr1", see
Chapter 7.18). Each of the interrupt sources can be individually masked in the
corresponding interrupt mask register. If the interrupt source is masked, the interrupt pin
MPIR1 will not be asserted when the corresponding event occurs.
MPIR2 is an auxiliary interrupt pin. The IWE8 provides two sets of 8 independent timers
in external RAM (timer set 1 and 2). Timer set 2 can be used independently from the rest
of the IWE8 driver software. When one of the timers of timer set 2 expires, a bit will be
set in the Interrupt Status Register 2 ("isr2", see Chapter 7.23) and MPIR2 will be
asserted.
Data Sheet
112
2003-01-20