PXB4219E Datasheet, PDF (125/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Memory Structure
4 to AAL0:
48 [aal0] = 1
4 to AAL1 unstructured CES:
47 [aal0] = 0, pcfN[p_ces] = 1
4 to AAL1 structured CES without CAS¹⁾:
47 [aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 0
4+Cb AAL1 structured CES with CAS²⁾:
to 46 [aal0] = 0, pcfN[p_ces] = 0, pcfN[p_cas] = 1
band_width band_width
N-1 Structured CES (with N = number of timeslots of the channel)
1F_H Unstructured CES (pcfN[p_ces] = 1)
sdt
SDT enable
X = If pcfN[p_ces] = 1 or [aal0] = 1
0 = Disabled
1 = Enabled
channel_
mode
Channel mode
00 = Inactive mode
01 = Active mode (normal mode)
10 = Standby mode
11 = Substitute mode
ref_slot
Reference slot indicator
1 = This slot is a reference slot
1) _{non-P format, cell may have only 46 user data octets in P format}
2) _{Cb: Required bytes for the CAS sub-block in an ATM cell}
Note: To allow IWE8 internal initialization, all channels must remain in inactive mode for
at least 250 µs after activation of the port (i.e. setting pcfN[p_rx_act] = 1). During
this time the device connected to the Framer Receive Interface has to be in normal
operation.
Note: If frame based SDT without CAS is used and filling level ≤ 45, the condition
band_width ≤ part_fill has to be fulfilled for correct operation.
Multiframe based SDT without CAS should not be used.
Data Sheet
125
2003-01-20