PXB4219E Datasheet, PDF (26/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
Table 2
UTOPIA Interface (36 pins) (cont’d)
Pin No. Symbol
Input (I) Function
Output (O)
V5, Y4, Y3, RXADR[4:0] I
U5, V4
PUA
UTOPIA Receive Address Bus
Five bit wide true data driven from the ATM
to MPHY layer to select the appropriate
MPHY device. RXADR[4] is the MSB.
U9, Y8,
W8, V8,
Y7, W7,
V7, Y6
TXDAT[7:0]
I
PUA
UTOPIA Transmit Data Bus
Byte-wide true data driven from ATM to
PHY layer. TXDAT[7] is the MSB.
V9
TXPTY
I
UTOPIA Transmit Odd Parity Bit
PUA
TXPTY is the odd parity bit over TXDAT[0:7]
driven by the ATM layer.
W6
TXSOC
I
UTOPIA Transmit Start-of-Cell
PDA
Active high signal asserted by the ATM
layer when TXDAT[0:7] contains the first
valid byte of the cell.
V6
TXCLAV
Slave: O UTOPIA Transmit Cell Available
Master: I Slave: TXCLAV is an active high signal
PDA
asserted by the PHY layer to indicate it can
accept data.
Master: TXCLAV is an active high signal
asserted by the ATM layer to indicate it can
accept data.
Y9
TXCLK
I
UTOPIA Transmit Clock
Data transfer/synchronization clock
provided by the ATM layer to the PHY layer
for synchronizing transfers on TXDAT[0:7].
Data Sheet
26
2003-01-20