PXB4219E Datasheet, PDF (105/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
5.2
UTOPIA Interface
IWE8
RXADR[0-4]
RXDAT[0-7]
RXPTY
RXSOC
RXCLAV
RXENB
RXCLK
UTOPIA
Receive
Interface
(Level 2)
TXADR[0-4]
TXDAT[0-7]
TXPTY
TXSOC
TXCLAV
TXENB
UTOPIA
Transmit
Interface
(Level 2)
TXCLK
Urati
Figure 29 UTOPIA Receive and Transmit Interfaces in Slave Mode
The UTOPIA receive and transmit interfaces are implemented according to the ATM
forum UTOPIA Level 2 Specification [6] and to the UTOPIA Level 1 Specification [5].
For UTOPIA level 2 compliant mode, the device is compatible to a PHY layer with 8 data
lines and 5 address lines.
In UTOPIA level 1 compliant mode the interface can be configured to ATM and PHY
layer with 8 data lines. In this case the address lines should be left unconnected.
According to the UTOPIA standard the ATM-Layer polls the PHY-Ports via the UTOPIA
address lines. If the address matches the programmed address range, the PHY controls
the flow of data via the TXCLAV or RXCLAV signal.
In transmit direction the PHY indicates via assertion of TXCLAV whether the
corresponding port is capable of accepting data. In case data can not be transferred to
the addressed port due to overrun of the programmed threshold of the port-specific cell
buffer, the TXCLAV won’t be activated.
In receive direction, RXCLAV is activated, if data is available at the addressed port.
Depending on the value of the “utmaster” bit in the “UTOPIA Configuration Register”
(“utconf”, see Chapter 7.34) the IWE8 will either act as an ATM -Layer (master mode)
or PHY-Layer (slave mode). As an ATM-Layer, the IWE8 can only work in UTOPIA level
1 compliant mode. As PHY Layer, IWE8 supports both, single PHY in UTOPIA level 1
compliant mode and single/multi PHY in UTOPIA level 2 compliant mode. The selection
between UTOPIA level 1 and level 2 can be done via the “utlevel” bit in “utconf”.
5.2.1 Port Addresses
The device can implement up to 8 PHY-Ports (= framer ports).
Data Sheet
105
2003-01-20