PXB4219E Datasheet, PDF (93/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
FTFRS[7:0]
RFCLK
0=
Structured CES: Depending on “p_tx_mfs” in
“pcfN”:
0 = Double frame mode: FTMFS is asserted every
2 frames (250 µs)
1=
E1 CRC multiframe mode: FTMFS is asserted
every 16 frames (2 ms)
T1 mode: every 3 ms
T1 superframe mode: every 1.5 ms
1=
Unstructured CES: Unused, constant low level
Framer Transmit Frame Synchronization Pulse
FTFRS is generated at the beginning of timslot 1 of every frame
Reference Clock
• Reference clock for the internal clock recovery circuit
• Depending on p_rx_em in pcfN: Optional emergency clock if
no transition on FRCLK is detected within 23 CLOCK cycles.
The segmentation continues using the RFCLK divided by four,
and using the byte-pattern programmed to a_emg_bpslct in
acfg for the cell payload.
The receive system clock and transmit system clock are both 8.192 MHz, and may be
independent from each other. The data rate is 2048 Mbit/s. This means that each bit lasts
for 4 clock cycles.
Data on the system internal highway is structured in frames of 256 bits every 125 µs. It
is transmitted in 32 slots numbered from 0 to 31 with slot 0 transmitted first. The data bits
of a slot are numbered from 1 to 8. The first transmitted bit ‘bit 1’ is the most significant
bit. Figure 23 shows the bit ordering.
Data Sheet
93
2003-01-20