PXB4219E Datasheet, PDF (115/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
5.6
External RAM Interface
The IWE8 needs to be connected to an external synchronous SRAM of 64k x 33 bits with
parity protection or 64k x 32 bits without parity protection.
For proper operation FT (Flow Through) SSRAM is needed. Pipelined SSRAM can not
be used, as this type has additional registered outputs.
A possible connection with 1 SRAM 64k x 36 component is shown in Figure 34.
.
IWE8
SRAM 64K x 36
RMCLK
CLK
RMADR[0-15]
A[0-15]
RMCS
CS
RMWR
WR
RMOE
OE
RMADC
ADSC
RMDAT[0-32]
D[0-35]
erc
Figure 34 External RAM Connection
The IWE8 has a fixed RAM interface cycle of 12 clock periods. A sequence of
6 consecutive read cycles (addresses AR1 to AR6), a dummy address cycle and
5 consecutive write cycles (addresses AW1 to AW5) is continuously repeated. The
timing of RMADC and RMOE is always fixed as shown in Figure 35. Whether the IWE8
reads data from the external RAM or writes data into the external RAM is controlled by
the RMCS and RMWR signals. In Figure 35, data R1 and R3 are actually read by the
IWE8, and data W1 and W3 are actually written into the external RAM.
Data Sheet
115
2003-01-20