PXB4219E Datasheet, PDF (71/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
Receive
Line
Clock
RTS
lpcr
0
RTS
0
1
generation
rtsi
10
1
lgc
ena
ena
2.43 MHz
0
32.768 MHzLoopback11
rtso
RTS
Transmit
FIFO
Frame
Generator
Clock
lprd lpru Recovery
Interface
0
1
0
SDI
1
lptu
Frame 1
Receiver 1 0
SDOR
Transmit
Line ¹
Clock ⁰
lc8
PLL
FILTER
PLL
PLL
SRTS
PLL
ACM
RTS
Receive
FIFO
1
0
lgs
Microprocessor Interface, Test and Control
RTS
Frame 1
Buffer Filling _{Receiver 2 0}
(ACM)
lptd
2.43 MHz Fractional
Divider
PDSYN
SDOD
SCLK
CLK52
RFCLK
Bdoti
Figure 19 Block Diagram of the ICRC
4.5.1 Data Flow
In transmit direction the ICRC generates RTS values for each port independently and
writes them into the RTS Transmit FIFO.
Received RTS values are written to the port specific RTS Receive FIFO to compensate
cell delay variation. RTS values for each port are processed at a frequency equal to the
SRTS period (8 cells). ACM values are processed immediately by the corresponding
PLL.
4.5.2 Frame Generator
This block generates 32-bit control frames that are used for communication with the rest
of the system.
For synchronization with the system the received synchronization signal PDSYN is used.
However, if this signal can’t be extracted from the received bit stream by the frame
receiver, the frames are generated by means of an internal synchronization counter.
The frame output is put in tristate during power down of the internal interface. As soon
as the internal synchronization counter is synchronized on PDSYN signal, the frame
output is enabled.
Data Sheet
71
2003-01-20