PXB4219E Datasheet, PDF (155/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Register Description
a_crv_en Clock recovery interface enable
0 = Disabled
1 = Enabled
a_dummy_
rts
Dummy RTS value
Dummy RTS value that will be transmitted in the first and second SRTS
period after start of segmentation.
a_emg_
bpslct
Emergency byte-pattern select
00 = Byte-pattern 0, defined in bp10[bp0] selected
01 = Byte-pattern 1, defined in bp10[bp1] selected
10 = Byte-pattern 2, defined in bp32[bp2] selected
11 = Byte-pattern 3, defined in bp32[bp3] selected
a_ovf_cnt_ Output queue overflow counter enable
en
0 = Disabled
1 = Enabled
a_ptr_prty SDT pointer even parity generation
0 = Disabled: Fixed value in bit 7 of pointer field: “0”.
1 = Enabled (recommended)
a_even_pck Even parity check for internal/external RAM and UTOPIA
0 = Odd parity check enabled (default operation)
The parity checkers expect the normal parity.
1 = Even parity check enabled
The parity checkers expect the inverse parity. This mode tests
the proper operation of the parity generators/checkers.
Data Sheet
155
2003-01-20