PXB4219E Datasheet, PDF (118/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
5.8
Master Clock
The basic processing time of an octet in the IWE8 is 12 clock cycles. As the time needed
to process one octet for each of the 8 ports must be less than the time required to transfer
one octet over a framer interface, this leads to the condition:
m × o × TCLOCK < f × b × TFramerClk
[15]
with:
m = 12 master-clock cycles needed for one octet per port
o = 8 ports
f = Framer-clock cycles per bit
b = 8 bits per octet
TClo
ck
>
--f---
12
×
TFr
ame
rClk
[16]
Table 29 Master Clock Frequency Depending on Mode
Mode
FAM, SYM8 and EC
GIM E1 and SYM2
GIM T1
T_CLOCK
F_CLOCK
< 1/3 x T_FramerCLK > 3 x F_FramerCLK = 3 x 8.192 MHz
< 1/12 x T_FramerCLK > 12 x F_FramerCLK = 12 x 2.048 MHz
< 1/12 x T_FramerCLK > 12 x F_FramerCLK = 12 x 1.544 MHz
Data Sheet
118
2003-01-20