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PXB4219E Datasheet, PDF (16/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines | |||
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IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Overview
â Internal clock recovery circuit using Synchronous Residual Time Stamp (SRTS, for
fully filled cells only) or Adaptive Clock Method (ACM) for unstructured CES ports.
For SRTS a patent fee needs to be paid. Optionally, itâs possible to order the PXB
4221 device, which comes without SRTS clock recovery.
â Trunk freezing and conditioning according to Bellcore TR-NWT-000170 [14]
⢠IMA interface:
â Programmable threshold between read and write pointer of Mapping Buffer
â Output Signal for buffer threshold crossing
â Output Signal for discarded cell
â Output pins for port number indication
⢠8 generic framer interfaces with integrated transmit clock selector supporting
â Synchronous Mode (SYM) for E1
â Generic Interface Mode (GIM)
â FALC Mode (FAM): Glue-less interface for Infineonâs Framer and Line Interface
Components (FALC)
â Echo Canceller Mode (EC): ATM cells are duplicated internally and transmitted via
two framer ports
⢠UTOPIA industry standard interface:
â Level 2 in slave mode; 8 data, 5 address lines
â Level 1 in master/slave mode
â UTOPIA clock up to 38.88 MHz
⢠16-bit generic microprocessor interface for control and configuration of the chip runs
either in Intel 386EX or Motorola compatible mode
⢠External synchronous Flow-Through SSRAM 1 x 64k x 33 bit or 1 x 64k x 32 bit
required
⢠Build-in data path loops for test
⢠Cell insertion/extraction via microprocessor interface
⢠3.3 Volt power supply with 5 Volt tolerant inputs
⢠Typical power dissipation 1 Watt
⢠P-BGA-256 package
⢠Temperature range from -40° to +85°C
Data Sheet
16
2003-01-20
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