PXB4219E Datasheet, PDF (44/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
octet 1
octet 2
octet 3
octet 4
GFC[3:0]/VPI[11:8] = prg_tx_hd[7:4]
VPI[7:4] = 0000_B
VPI[3:0] = 0000_B
VCI[15:12] = 0000_B
VCI[11:4] = 0000_0000_B
VCI[3:0] = 0000_B
PTI[2:0] = prg_tx_hd[3:1] CLP =
prg_tx_
hd[0]
octet 5
UDF
octet 6
prg_tx_pl[7:0]
.
.
octet 53
prg_tx_pl[7:0]
• If idle cell insertion according to ITU-T I.361 or ITU-T I.432.1 is desired, the
“prg_tx_hd” field of “txid” should be set to 0000_0001_B.
• If unassigned cell insertion at the NNI or uncontrolled UNI according to ITU-T I.361 is
desired, the “prg_tx_hd” field of “txid” should be set to 0000 XXX0. For X any value is
allowed.
The payload of idle or unassigned cells consists of the same octet which is repeated 48
times. It is programmable by the “prg_tx_pl” field of the “txid” register.
• For ITU-T I.432.1 compliant idle cells, the “prg_tx_pl” field of “txid” should be set to
0110_1010_B.
• The pre-assigned values of the information field of all unassigned cells are for further
study (ITU-T I.361 [30])
4.1.1.4 Cell Payload Scrambling
ITU-T I.432.3 [34] recommends the self-synchronizing scrambler x⁴³+1 for payload
scrambling at E1 datarates. For T1 no scrambling is recommended, which the IWE8
supports.
The scrambler function is implemented in the device. It can be disabled per port by the
x43_scrambling bit in the “ATM Transmit Reference Slot” in RAM2.
4.1.1.5 HEC Generation
The HEC generation is implemented according to ITU-T I.432.1 [33] using the generator
polynomial x⁸ + x² + x + 1. To significantly improve the cell delineation performance in
the case of bit-slips it is recommended that
• the check bits are added (modulo 2) to an 8-bit pattern (coset) before being inserted
in the last octet of the header.
• the recommended pattern is “0101 0101".
Data Sheet
44
2003-01-20