PXB4219E Datasheet, PDF (91/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
5
Interface Description
5.1
Generic Framer Interface
The selection of the Echo Canceller mode is done via an external pin (Pin EC = 0).
In standard mode (Pin EC = 1), 4 sub modes can be selected via the “om” bits in the
Operation Mode Register (“opmo”, see Chapter 7.24)
• FALC mode (FAM)
• Generic Interface mode (GIM)
• Synchronous mode with an external reference clock of 8 MHz (SYM8)
• Synchronous mode with an external reference clock of 2 MHz (SYM2)
Depending on the level of the E1/T1 pin FAM and GIM can run based on E1 or T1
frames. SYM2 and SYM8 will always use E1 frame formats.
A clock selector for the Framer transmit clock is integrated in the IWE8. Depending on
bits “ftckn” in the FT Clock Select Register (“ftcs”, see Chapter 7.25) selection between
the following clocks is done:
• the line clock FRCLK
• the SRTS regenerated clock from internal or external clock recovery circuit
• the clock derived from the external reference clock (pin RFCLK).
The data on the Generic Framer Interface is structured in frames repeated every 125µs.
Each frame is divided into timeslots, where the least sigificant slot is transmitted first. The
data bits in each slot are transmitted starting with the most significant bit.
5.1.1 FALC Mode (FAM)
The IWE8 can be directly connected to Infineon’s “Framer and Line interface
components” (FALC) as shown in Figure 22.
QuadFALC^TM
SCLKR
RDO
SYPR
RMFB
FREEZE
IWE8
FRCLKn
FRDATn
FRFRSn
FRMFBn
FRLOSn
Figure 22
XMFS
SYPX
XDI
SCLKX
Connection of IWE8 to QuadFALC
FTMFSn
FTFRSn
FTDATn
FTCKOn
Data Sheet
91
Coitf
2003-01-20