PXB4219E Datasheet, PDF (10/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
List of Figures
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Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Typical IWE8 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Line Card for 8 T1/E1 Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Echo Canceller Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Cell delineation state diagram (Figure 5/I.432.1) . . . . . . . . . . . . . . . . . 47
Maintenance state transitions for cell delineation (Figure 2/ I.432.3). . 47
HEC: Receiver mode of Operation (Figure 3/ITU I.432.1) . . . . . . . . . . 48
HEC Detection According to ATM Forum . . . . . . . . . . . . . . . . . . . . . . 49
Pre-assigned cell header values at the UNI (Table 1/I.361) . . . . . . . . 50
Pre-defined header field values [11] . . . . . . . . . . . . . . . . . . . . . . . . . . 50
SAR-PDU of AAL Type 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Synchronization of SRTS Generation with the Start of Segmentation . 57
Reassembly Buffer Initialization: No CDV . . . . . . . . . . . . . . . . . . . . . . 64
Reassembly Buffer Initialization: positive CDV at Start Up . . . . . . . . . 65
Reassembly Buffer Initialization: Negative CDV at Start Up . . . . . . . . 66
Reassembly Buffer Initialization for SDT: positive CDV at Start Up. . . 67
Block Diagram of the ICRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Transient Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Influence of Damping on Lock in Time. . . . . . . . . . . . . . . . . . . . . . . . . 77
Connection of IWE8 to QuadFALC . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Framer Interface in FAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Framer Interface in GIM T1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Framer Interface in GIM E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Framer Interface in SYM2 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Framer Interface in SYM8 E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Framer Interface in EC Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
UTOPIA Receive and Transmit Interfaces in Slave Mode . . . . . . . . . 105
Utopia Sideband Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
IMA Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Connection of IWE8 to an Intel Type Microprocessor . . . . . . . . . . . . 113
Connection of IWE8 to an Motorola Type Microprocessor . . . . . . . . 114
External RAM Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
RAM Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Memory Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Structure of the IWE8 external RAM . . . . . . . . . . . . . . . . . . . . . . . . . 137
Clock Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226
ACM Jitter Tolerance in E1 Mode without Jitter Attenuator . . . . . . . . 230
ACM Jitter Tolerance in E1 Mode with Jitter Attenuator . . . . . . . . . . 231
ACM Jitter Tolerance in T1 Mode without Jitter Attenuator . . . . . . . . 232
ACM Jitter Tolerance in T1 Mode with Jitter Attenuator . . . . . . . . . . 232
Data Sheet
10
2003-01-20