PXB4219E Datasheet, PDF (57/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Operational Description
The RTS value stored in the RTS buffer of the port is loaded from the Internal Clock
Recovery Circuit ICRC or from the Clock Recovery Interface. A new value will be
provided by the ICRC once every cycle of 8 cells. To guarantee that the value stored in
the RTS buffer of the port is correct, the procedure indicated in Figure 14 is followed.
Start of
Segmentation
1st Cycle of 8 Cells;
Dummy RTS Value Transmitted
01234567
2nd Cycle of 8 Cells;
Dummy RTS Value Transmitted
3rd Cycle of 8 Cells;
1st RTS Value Transmitted
Reset of RTS
generator
1st RTS Value
Received
2nd RTS Value
Received
sorgwsos
Figure 14 Synchronization of SRTS Generation with the Start of Segmentation
After the start of segmentation, during the 1st cycle of 8 cells, the RTS generator of the
corresponding port is reset. If an external clock recovery circuit is used, it is reset by
writing a reset frame for the corresponding port on the Clock Recovery Interface. During
this cycle a dummy RTS value is transmitted.
During the 2nd cycle of 8 cells, the IWE8 expects to receive the first valid RTS value
while transmitting a dummy RTS value.
During the following cycles of 8 cells the RTS value received in the previous cycle will be
transmitted.
The dummy RTS value is programmable with “a_dummy_srts” in the register “acfg” and
is common for all ports. It must be programmed before the a_crv_en bit in “acfg” is made
active. Otherwise the first 2 RTS values transmitted will be fixed at “0000”.
If the ICRC does not provide new RTS values to the RTS Transmit Buffer (buffer
underflow), the last received value is repeated. If too many RTS values are provided
(buffer overflow), the values in excess will be omitted and a “rts_overflow” bit in the
Extended Interrupt Status Register 2 “eis2” is set.
Data Sheet
57
2003-01-20