PXB4219E Datasheet, PDF (28/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

2.2.4
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Pin Descriptions
Clock Recovery Interface
Table 4
Pin No.
Y18
Y20
W20
T17
T20
Clock Recovery Interface
Symbol
Input (I) Function
Output (O)
SDI
I
Serial Data Input
Clock recovery frame input.
SDOD
O
Tri
Serial Data Output Data
Clock recovery frame output
SDOR
O
Tri
Serial Data Output Reset
Clock recovery reset frame output
SSP
O
Serial Synchronization Pulse
Tri
Frame synchronization pulse output
SCLK
O
Serial Clock
Tri
Clock output of the clock recovery interface.
Runs at the same frequency than the
CLOCK input
2.2.5 Microprocessor Interface
Table 5
Microprocessor Interface
Pin No. Symbol
Input (I) Function
Output (O)
K1, K3, K2, MPDAT[15:0]
J1, J2, J3,
J4, H1, H2,
H3, G1,
G2, G3, F1,
F2, G4
I/O
PUA
Microprocessor Data Bus
This bidirectional three-state bus provides
the general-purpose data path between the
IWE8 and an external master. The bus uses
little endian word order. MPDAT15 is the
MSB.
T4, V1, U2, MPADR[17:0] I
T3, U1, T2,
R3, P4, T1,
R2, P3, R1,
P2, P1, N3,
N2, N1, M4
Microprocessor Address Bus
Provides the address of the current bus
cycle. Addresses are 16-bit aligned.
MPADR17 is the MSB of the bus
E2
MPCS
I
Microprocessor Chip Select
This signal is driven by the bus master to
indicate a read or write access.
Data Sheet
28
2003-01-20