PXB4219E Datasheet, PDF (92/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
The data is transferred between the FALC and the IWE8 via a system internal highway.
FRCLK[7:0]
FRDAT[7:0]
FRMFB[7:0]
FRFRS[7:0]
FRLOS[7:0]
FTCKO[7:0]
FTDAT[7:0]
FTMFS[7:0]
Framer Receive Clock
Receive system clock of 8.192 MHz (falling)
Framer Receive Data
FRDAT is sampled in the middle of the bit period on the falling
edge of FRCLK
Framer Receive Multiframe Begin
Depending on bits “p_ces” in “pcfN”:
0=
Structured CES: A pulse on this pin designates the
first frame of a new multiframe
1=
Unstructured CES: Unused
FRMFB is always sampled with the falling edge of FRCLK. If the
framing is incorrect, the IWE8 stays in hunt mode.
Framer Receive Frame Synchronization Pulse
FRFRS is generated at the beginning of timslot 1 of each frame
Framer Receive Loss of Signalling
Framer Transmit Clock
depending on bits ftckn in ftcs:
00 =
depending on bit “rts_eval” in “opmo”:
0 = Transmit clock input with 8.192 MHz (falling)
1 = Clock of ICRC is used as transmit clock and is
also switched to FTCKO pins (FTCKO is output
pin)
01 =
FRCLK (“rts_eval” = 1)
10 =
Clock derived from RFCLK(“rts_eval” = 1)
11 =
No clock (“rts_eval” = 1)
Framer Transmit Data
FTDAT is clocked with the falling edge of FTCKO:
Framer Transmit Multiframe Synchronization
Depending on bit p_ces in pcfN:
Data Sheet
92
2003-01-20