PXB4219E Datasheet, PDF (101/290 Pages) Infineon Technologies AG – Interworking Element for 8 E1/T1 Lines

FRFRS[7:0]
FRLOS[7:0]
FTCKO[7:0]
FTDAT[7:0]
FTMFS[7:0]
FTFRS[7:0]
RFCLK
IWE8, V3.4
PXB 4219E, PXB 4220E, PXB 4221E
Interface Description
0=
FRMFB is active low
1=
FRMFB is active high
depending on bit “symn” in “opmo”:
0=
FRMFB[0] is used for frame and multiframe
synchronization in receive and transmit direction of
all ports. FRMFB[1:7] are unused
1=
FRMFB[N] is used for frame and multiframe
synchronization in receive and transmit direction of
corresponding ports
FRMFB is always sampled with the opposite clock-edge of
FRDAT.
Framer Receive Frame Synchronization Pulse
Unused
Framer Receive Loss of Signalling
Framer Transmit Clock
Unused
Framer Transmit Data
depending on bit “frri” in “opmo”:
0=
FTDAT is clocked with the rising edge of RFCLK
1=
FTDAT is clocked with the falling edge of RFCLK
Framer Transmit Multiframe Synchronization
Unused
Framer Transmit Frame Synchronization Pulse
Unused
Reference Clock
Central framer interface clock with 2.048 MHz
RFCLK
FRDATn
FRMFB
B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
FTDATn B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 B3 B4 B5 B6 B7 B8
248 249 250 251 252 253 254 255 256 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
timeslot 31
timeslot 0
timeslot 1
FRDATn sampled with rising edge of RFCLK
Fisym2e1
Figure 26 Framer Interface in SYM2 E1
Data Sheet
101
2003-01-20