C5ENPB0-DS Datasheet, PDF (99/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
99
BMU Timing
Specifications
The BMU timing specifications are shown in Figure 24 and described in Table 53.
The BMU synchronous DRAM interface is PC100-compliant and designed to work with
industry standard SDRAM components with 12 or fewer address lines. The information
below is intended to provide the output, setup, and hold data required to design this
interface without duplicating the transaction waveform diagrams in SDRAM data sheets.
Figure 24 BMU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
MDCLK
T_mc
M_ctl
T_mco
MAn
T_mao
MDn
(output)
MDn
(input)
T_mdo
T_mdz
T_mdv
T_mds
T_mdh
Table 53 BMU Timing Description
SYMBOL PARAMETER
MIN TYP
Tmc
BMU Cycle Time
7.5
Tmco BMU Ctrl Output
0.8
Tmao BMU Addr Output
0.8
Tmds BMU Data Setup
0.5
Tmdh BMU Data Hold
1.1
Tmdo BMU Data Output
0.8
Tmdz BMU Data Clk to Tri*
0.8
Tmdv BMU Data Clk to Driven* 0.8
Tr, Tf MDCLK Rise, Fall
MAX UNIT
ns
3.5 ns
3.7 ns
ns
ns
4.4 ns
4.4 ns
4.4 ns
2.0 † ns
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08