C5ENPB0-DS Datasheet, PDF (101/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications 101
Table 55 TLU Timing Description (continued) (continued)
SYMBOL PARAMETER
MIN TYP
Ttdo
TLU Data Output
0.8
Ttdz
TLU Data Clk to Tri*
0.8
Ttdv
TLU Data Clk to Driven* 0.8
Tr, Tf
TCLKI Rise, Fall
* _{Not fully tested, values based on design/characterization.}
† _{Measured 0.8V to 2.0V.}
MAX UNIT
4.5 ns
4.5 ns
4.5 ns
2.0 † ns
Table 56 Signal Groups in TLU Timing Diagrams
SIGNAL GROUP
Control (T_ctl)
Address (TAn)
Data (TDn)
INCLUDED SIGNALS
TCE0X - TCE3X, TWE0X - TWE3X
TA0 - TA21
TD0 - TD63, TPAR0-3
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08