C5ENPB0-DS Datasheet, PDF (40/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

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CHAPTER 2: SIGNAL DESCRIPTIONS
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example
SIGNAL NAME* PIN #† TOTAL TYPE
CPn_0
Table 7 1
LVTTL
I/O LABEL
O_PD TCLK
CPn_1
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
CPn+1_0
CPn+1_1
CPn+1_2
CPn+1_3
CPn+1_4
CPn+1_5
CPn+1_6
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
CPn+3_0
CPn+3_1
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc_PU nc
O_PD TXD(9)
O_PU TXD(8)
O_PD TXD(7)
O_PU TXD(6)
O_PU TXD(1)
nc_PD nc
nc_PU nc
O_PD TXD(5)
O_PU TXD(4)
O_PD TXD(3)
O_PU TXD(2)
O_PU TXD(0)
nc_PD nc
I_PU RCLK
I_PD RXD(9)
I_PU RXD(8)
I_PD RXD(7)
I_PU RXD(6)
I_PU RXD(1)
nc_PD nc
I_PU RCLKN
I_PD RXD(5)
I_PU RXD(4)
I_PD RXD(3)
I_PU RXD(2)
I_PU RXD(0)
SIGNAL DESCRIPTION
Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
nc
Transmit Data (ten bits wide, last on wire)
Transmit Data
Transmit Data
Transmit Data
Transmit Data
nc
nc
Transmit Data
Transmit Data
Transmit Data
Transmit Data
Transmit Data (ten bits wide, first on wire)
nc
Receive Clock (62.5 MHz)
Receive Data (ten bits wide, last on wire)
Receive Data
Receive Data
Receive Data
Receive Data
nc
Receive Clock Inverted
Receive Data
Receive Data
Receive Data
Receive Data
Receive Data (ten bits wide, first on wire)
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR