C5ENPB0-DS Datasheet, PDF (95/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
95
Low Speed Serial Interface Timing Specifications
The low speed serial interface timing is shown in Figure 21 and described in Table 50.
Figure 21 Low Speed Serial Interface Timing Diagram
SICL
SIDA
Cycle 2
T_slss T_slhs T_slhd T_slsd
Cycle 3
T_slc
T_slst
T_slb
Table 50 Low Speed Serial Interface Timing Description
SYMBOL
Tslc
Tslss
Tslhs
Tslsd
Tslhd
Tslst
Tslb
Cmax
PARAMETER
SICL Cycle Time
Set-up Time for Repeated START Condition
Hold Time START Condition
Data Set-up Time
Data Hold Time
Set-up Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Capacitive load for each line of the bus
MIN MAX UNIT
2500
ns
600
ns
600
ns
250
ns
0.0
ns
600
ns
1250
ns
400 pF
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08