C5ENPB0-DS Datasheet, PDF (80/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Thermal Management
Information
This section provides thermal management information for the ceramic ball grid array
(CBGA) package for air-cooled applications. Proper thermal control design is primarily
dependent on the system-level design—the heat sink, airflow, and thermal interface
material. To reduce the die-junction temperature, heat sinks may be attached to the
package by several methods—spring clip to holes in the printed-circuit board or package,
and mounting clip and screw assembly (refer to Figure 10); however, due to the potential
large mass of the heat sink, attachment through the printed circuit board is suggested. If a
spring clip is used, the spring force should not exceed 5.5 pounds.
Figure 10 Package Cross Section View with Several Heat Sink Options
Heat Sink
Heat Sink Clip
Thermal Interface Material
CBGA Package
C5ENPB0-DS REV 08
Printed Circuit Board
Internal Package Conduction Resistance
For the exposed-die packaging technology the intrinsic conduction thermal resistance
paths are as follows:
• The die junction-to-case (or top-of-die for exposed silicon) thermal resistance
• The die junction-to-ball thermal resistance
Figure 11 depicts the primary heat transfer path for a package with an attached heat sink
mounted to a printed-circuit board.
FREESCALE SEMICONDUCTOR