C5ENPB0-DS Datasheet, PDF (84/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

84
CHAPTER 3: ELECTRICAL SPECIFICATIONS
Clock Timing
Specifications
Cycle 1
The system clock timing is shown in Figure 13 and described in Table 41.
Figure 13 System Clock Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
SCLK
SCLKX
T_sc
T_sh
T_sl
CCLKn
T_ccN
T_cch
T_ccl
Table 41 System Clock Timing Description
SYMBOL PARAMETER
MIN
Tsc
System Cycle Time 3.76
Tsc
System Cycle Time 3.33
Tsh Sys Clk High Pulse 45
Tsl
Sys Clk Low Pulse 45
Tcc0 CCLK0 Cycle Time
Tcc1 CCLK1 Cycle Time
Tcc2 CCLK2 Cycle Time
Tcc3 CCLK3 Cycle Time
Tcc4 CCLK4 Cycle Time
Tcc5 CCLK5 Cycle Time
Tcc6 CCLK6 Cycle Time
Tcc7 CCLK7 Cycle Time
Tcch CCLKm High Time 40%
Tccl CCLKm Low Time 40%
TYP MAX
55
55
647.67
488.28
29.097
22.353
20.00
9.412
8.00
6.43
60%
60%
UNIT COMMENT
ns 266MHz core clock
ns 300MHz core clock
Duty cycle*
Duty cycle*
ns T1†
ns E1†
ns E3†
ns T3†
ns RMII†
ns Fibre Channel†
ns GMII†
ns OC-3†
% cycle pulse is high
% cycle pulse is low
* _{Pulse duty cycle measured at crossing voltage of SCLK/SCLKX}
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR