C5ENPB0-DS Datasheet, PDF (46/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

46
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 17 PROM Interface Signals (continued)
SIGNAL
NAME
SPLD
PIN #
Y3
TOTAL TYPE I/O
1
LVTTL O
SPCK
Y4
TOTAL PINS
1
LVTTL O
4
SIGNAL DESCRIPTION
When load is asserted on a positive clock
edge, the external logic performs a parallel
load. On each positive clock edge when
load is de-asserted, the shift registers shift.
When the PROM interface is idle:
• If SPLD is asserted HI it indicates low
speed serial protocol,
• If asserted LOW it indicates MDIO serial
protocol.
Clock
Figure 5 shows the connections between the PROM Interface and external board logic.
The application is required to provide an external shift register with parallel-in and
parallel-out capabilities, and a parallel load register. Both devices should be
positive-edge-triggered and perform a parallel load whenever SPLD is asserted. When
SPLD is deasserted the shift register shifts.
Figure 5 PROM Interface Diagram
C-5e Network Processor External Logic
21
0
PROM_ADDR<21:1> CE
SPDO
21
1
21
6
0
21
60
SPDI
Internal Shift
15
Register
31
16 15
0
PROM _H_Word PROM _LO_Word
PROM _Return_Data
PROM Clock Gen.
SPCLK
PROM Sequencer ^SPLD
External Shift
Register
21
0
PROM_ADDR<21:1> CE
21
1 16
PROM _{PROM_Data}
C5ENPB0-DS REV 08
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