C5ENPB0-DS Datasheet, PDF (92/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

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CHAPTER 3: ELECTRICAL SPECIFICATIONS
Executive Processor
Timing Specifications
The XP timing specifications include:
• PCI Timing Specifications
• MDIO Serial Interface Timing Specifications
• Low Speed Serial Interface Timing Specifications
• PROM Interface Timing Specifications
PCI Timing Specifications
The PCI timing is shown in Figure 19 and described in Table 48.
Cycle 1
Figure 19 PCI Timing Diagram
Cycle 2
Cycle 3
Cycle 4
PCLK
PAD/P_ctl
(output)
T_pao
PAD/P_ctl
(input)
PGNTX
(input)
PIDSEL
(input)
T_pc
T_paz
T_pav
T_pas T_pah
T_pgs T_pgh
T_pis T_pih
Cycle 5
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR