C5ENPB0-DS Datasheet, PDF (50/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

50
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 19 Fabric Interface Signals (continued)
SIGNAL NAME
FOUT0 - FOUT31
FRXCLK
FTXCLK
FRXCTL0 - FRXCTL6
FTXCTL0 - FTXCTL6
TOTAL PINS
PIN #
AJ18, AH18, AG18, AE18, AD18, AC18, AJ17,
AH17, AF17, AE17, AD17, AC17, AJ16, AH16,
AG16, AF16, AE16, AD16, AC16, AJ15, AG15,
AF15, AD15, AC15, AJ14, AH14, AG14, AF14,
AE14, AD14, AC14, AJ13
AC6
AG12
AE7, AD7, AC7, AJ6, AG6, AF6, AD6
AH13, AF13, AE13, AD13, AC13, AJ12, AH12
TOTAL TYPE I/O SIGNAL DESCRIPTION
32 LVTTL O Fabric Data Bus Out
1
LVTTL I_PD Receive Clock
1
LVTTL I_PD Transmit Clock
7
LVTTL I_PD, O Receive Control Signals
7
LVTTL I_PD, O Transmit Control Signals
80
The following tables list the Fabric Interface pin mappings:
• Utopia1, Utopia2, Utopia3 ATM Mode mappings are listed in Table 20
• Utopia1, Utopia2, Utopia3 PHY Mode mappings are listed in Table 21
• PRIZMA Mode mappings are listed in Table 22 (PRIZMA protocol is a subset of Utopia3
PHY)
• Power X(CSIX-L0) Mode mappings are listed in Table 23
• CSIX-L1 Mode mappings are listed in Table 24
Table 20 Utopia1*, 2*, 3 ATM Mode, C-5e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FRXCTL0
Output
FRXCTL1
FRXCTL2
Input
Input
UTOPIA
RxEnb*
RxClav
RxSOC
NOTE
Pullup or No
Connection
TRANSMIT SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FTXCTL0
Output
FTXCTL1
FTXCTL2
Input
Output
UTOPIA
TxEnb*
TxClav
TxSOC
NOTE
Pullup or No
Connection
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR