C5ENPB0-DS Datasheet, PDF (87/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
87
GMII / TBI Tx
CPn_0 (TCLK)
CPn_2-6 (Tx)
CPn+1_2-6 (Tx)
Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
The Gigabit GMII Ethernet interface timing is shown in Figure 16 and described in
Table 44. The TBI interface timing is shown in Figure 16 and described in Table 45.
Figure 16 Gigabit Ethernet and TBI Interface Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_cgt
T_cgo
MII Tx
MII CPn_1 (TCLKI)
MII CPn_2-6 (Tx)
Cycle 1
Cycle 2
T_cmt
T_cmo
Cycle 3
TBI Rx
CPn+2_1 (RCLK)
CPn+3_1 (RCLKN)
CPn+2_2-6 (Rx)
CPn+3_2-6 (Rx)
GMII/MII Rx
CPn+2_1 (RCLK)
CPn+2_2-6 (Rx)
CPn+3_1-6 (Rx)
Cycle 1
Cycle 2
Cycle 3
T_ctr
T_ctd
T_cts T_cth
Cycle 1
Cycle 2
Cycle 3
T_cgr
T_cgs T_cgh
Cycle 4
Cycle 4
Cycle 5
Cycle 5
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08