C5ENPB0-DS Datasheet, PDF (86/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

86
CHAPTER 3: ELECTRICAL SPECIFICATIONS
CPn_0 (TCLK)
CPn_2/3/6 (Tx)
CPn_1/4/5 (Rx)
Table 42 DS1/DS3 Ethernet Timing Description
SYMBOL
Tcdt
Tcdo
Tcdr
Tcds
Tcdh
PARAMETER
DS1/DS3 Transmit Cycle Time
DS1/DS3 Output Time
DS1/DS3 Receive Cycle Time
DS1/DS3 Setup Time
DS1/DS3 Hold Time
MIN TYP
MAX
UNIT
647/22.4
ns
3.0/3.0
400/15.0 ns
647/22.4
ns
2.0
ns
0
ns
10/100 Ethernet Timing Specifications
The 10/100 Ethernet interface timing is shown in Figure 15 and described in Table 43.
Figure 15 10/100 Ethernet Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_cet
T_ceo
T_ces Tceh
Table 43 10/100 Ethernet Timing Description
SYMBOL PARAMETER
MIN TYP
Tcet
Transmit Cycle Time*
20
Tceo Output Time
3.0
Tces
Setup Time
2.0
Tceh Hold Time
0
* _{STD/Fast Ethernet}
MAX UNIT
ns
15.0 ns
ns
ns
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR