C5ENPB0-DS Datasheet, PDF (51/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
51
Table 20 Utopia1*, 2*, 3 ATM Mode, C-5e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-5e NETWORK
PROCESSOR
FRXCTL3
I/O
Input
UTOPIA
n/a
NOTE
FRXCTL4
Input
n/a
FRXCTL5
FRXCTL6
Input
Input
n/a
RxPrty
* _{Cell size must be 4Byte aligned. Both RxEnb and TxEnb are Active Low.}
TRANSMIT SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FTXCTL3
Input
FTXCTL4
Input
FTXCTL5
Input
FTXCTL6
Output
UTOPIA
n/a
n/a
n/a
TxPrty
NOTE
Table 21 Utopia1*, 2*, 3 PHY Mode, C-5e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FRXCTL0
Input
FRXCTL1
Output
FRXCTL2
Input
FRXCTL3
Input
FRXCTL4
Input
FRXCTL5
Input
FRXCTL6
Input
UTOPIA
TxEnb*
TxClav
TxSOC
n/a
n/a
n/a
TxPrty
NOTE
Pullup
No Connection
TRANSMIT SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FTXCTL0
Input
FTXCTL1
Output
FTXCTL2
Output
FTXCTL3
Input
FTXCTL4
Input
FTXCTL5
Input
FTXCTL6
Output
* _{Cell size must be 4Byte aligned. Both TxEnb and RxEnb are Active Low.}
UTOPIA
RxEnb*
RxClav
RxSOC
n/a
n/a
n/a
RxPrty
NOTE
Pullup
No Connection
When configuring two C-5e network processors back-to-back using the Fabric Port, set
up the transmit side of each C-5e network processor in Utopia ATM mode and the receive
side of each C-5e network processor in Utopia PHY mode.
Table 22 PRIZMA Mode, C-5e Network Processor to Fabric Interface Pin Mapping
RECEIVE SIGNALS
C-5e NETWORK
PROCESSOR
I/O
FRXCTL0
Input
UTOPIA
TxEnb*
TRANSMIT SIGNALS
NOTE
C-5e NETWORK
PROCESSOR
I/O
Not connected to FTXCTL0
fabric.
Input
UTOPIA
RxEnb*
NOTE
Not connected to
fabric.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08