C5ENPB0-DS Datasheet, PDF (103/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications 103
Table 57 QMU SRAM (Internal Mode) Timing Description (continued)
SYMBOL PARAMETER
MIN TYP MAX UNIT COMMENT
Tqdz QMU Data Clk to Tri* 0.9
4.0 ns
Tqdv QMU Data Clk to 0.9
Driven*
4.0 ns
Tr, Tf QACLKI Rise, Fall
2.0 † ns
* _{Not fully tested, values based on design/characterization.}
† _{Measured 0.8V to 2.0V.}
Table 58 Signal Groups in QMU SRAM (Internal Mode) Timing Diagrams
SIGNAL GROUP
Control (Q_ctl)
Address (QAn)
Data (QDn)
INCLUDED SIGNALS
QWEX
QA0-QA16
QD0-QD31, QDPL, QDPH
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08