C5ENPB0-DS Datasheet, PDF (49/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
49
Table 18 General System Interface Signal
SIGNAL NAME
XPUHOT
PIN # TOTAL TYPE I/O
W8 1
LVTTL I_PD
TOTAL PINS
1
SIGNAL DESCRIPTION
Sample at Power On Reset determines if the XP RISC Core is held in reset. Low
equals reset and High equals active. During normal operation, this is an
external interrupt, triggered asynchronously on the rising edge of XPUHOT.
Fabric Processor Interface
Signals
The FP has logical signal interfaces: a receive data interface and a transmit data interface,
each with its own control, data, and clock signals. The interface has the following
characteristics:
• The interface clocks, FRXCLK and FTXCLK can have a different frequency from the core
C-5e NP clock frequency. The FP supports a fabric interface frequency from 10MHz to
125MHz.
• FRXCLK and FTXCLK can be independent of each other; typically they have the same
frequency, but are allowed to be skewed relative to each other.
• Each data bus can be configured for widths of 8 (data bits 7:0 are used), 16 (bits 15:0),
or 32 (bits 31:0). In 8bit mode, data bits 31:8 are unused. In 16bit mode, data bits 31:16
are unused.
Table 19 Fabric Interface Signals
SIGNAL NAME
FIN0 - FIN31
PIN #
TOTAL TYPE I/O SIGNAL DESCRIPTION
AE12, AD12, AC12, AJ11, AH11, AG11,AF11, 32
AE11, AD11, AC11, AJ10, AG10, AF10, AD10,
AC10, AJ9, AH9, AG9, AF9, AE9, AD9, AC9, AJ8,
AH8, AG8, AF8, AE8, AD8, AC8, AJ7, AH7, AG7
LVTTL I_PD Fabric Data Bus In
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08