C5ENPB0-DS Datasheet, PDF (28/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

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CHAPTER 1: FUNCTIONAL DESCRIPTION
Queue Management Unit
The Queue Management Unit (QMU) autonomously manages a number of
application-defined descriptor queues. It handles inter-CP and inter-C-5e NP descriptor
flows by providing switching and buffering. It also performs descriptor replication for
multicast applications. A number of up to 128 queues can be assigned to each CPRC for
QoS-based services.
The QMU provides a queuing engine internal to the chip and uses external SRAM to store
the descriptors. Scheduling is done by the CPs. The QMU supports up to 512 queues and
16, 384 descriptor buffers. A descriptor buffer holds an application-defined “descriptor”,
which is a structure that defines the payload buffer handle and other attributes of the
forwarded cell or packet.
The QMU’s external SRAM interface uses ZBT synchronous SRAMs organized in a single
bank of up to 128k, 32bit words. This interface runs at up to 160MHz frequency (refer to
Table 57 on page 102 for details).
The C-5e provides two (2) modes for managing queues. They consist of:
• Internal Mode (using the internal QMU only)
• External Mode
Although the C-5e NP provides an external mode, it does not support an external traffic
manager device.
See the C-5e/C-3e Network Processor Architecture Guide (part number C5EC3EARCH-RM) for
more details.
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR