C5ENPB0-DS Datasheet, PDF (43/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
43
Table 14 OC-12 Signals Example (continued)
SIGNAL NAME* PIN #† TOTAL TYPE I/O
CPn+3_5
CPn+3_6
TOTAL PINS
Table 7 1
Table 7 1
28
LVTTL I_PU
nc
nc_PU
* _{n can be 0, 4, 8, or 12}
† _{Reference Table 7 for pin numbers for a different cluster.}
LABEL
RXD(7)
nc
SIGNAL DESCRIPTION
Receive Data (most significant bit)
nc
Executive Processor
System Interface Signals
The XP’s system interface manages the supervisory controls for the network interfaces, as
well as the set of pins that provide interfaces to other components in the system that are
not memories or network interfaces. It is also the primary interface used for initializing the
C-5e NP after reset. The XP signals include PCI signals, Serial interface signals, and PROM
interface signals.
PCI Signals
The PCI can be configured to support a 32bit PCI capable of operating at either 33MHz or
66MHz. The PCI is fully compliant with PCI Specification revision 2.1. Table 15 describes
the PCI signals.
Table 15 PCI Signals
SIGNAL NAME
PAD0 - PAD31
PCBEX0 - PCBEX3
PIN #
TOTAL TYPE
AJ5, AJ4, AJ3, AJ2, AJ1, AH5, AH4, 32 PCI
AH3, AH1, AG5, AG4, AG3, AG2,
AG1, AF5, AF4, AF2, AF1, AE5,
AE4, AE3, AE1, AD5, AD4, AD3,
AD2, AD1, AC5, AC4, AC3, AC2,
AC1
AB6, AB5, AB4, AB2
4
PCI
I/O SIGNAL DESCRIPTION
I/O Multiplexed Address/Data Bus. These signals are
multiplexed address and data bits. The C-5e NP
receives addresses as target and drives addresses as
master. It drives the data and receives read data as
master.
I/O Command byte enables. These signals are
multiplexed command and byte enabled signals.
The C-5e NP receives byte enables as target and drives
byte enables as master.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08