C5ENPB0-DS Datasheet, PDF (91/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
91
CPn_1 (TCLKI)
CPn_0 (TCLK)
CPn_2-6 (Tx)
CPn+1_2-5 (Tx)
CPn+2_1 (RCLK)
CPn+2_2-6 (Rx)
CPn+3_2-5 (Rx)
Cycle 1
OC-12 Timing Specifications
The OC-12 interface timing is shown in Figure 18 and described in Table 47.
Figure 18 OC-12 Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_c12i
T_c12d
T_c12t
Cycle 1
T_c12o
Cycle 2
T_c12r
T_c12s T_c12h
Table 47 OC-12 Timing Description
SYMBOL
Tc12i
Tc12d
Tc12t
Tc12o
Tc12r
Tc12s
Tc12h
PARAMETER
OC-12 Transmit Cycle Time*
OC-12 Clock Duty Cycle
OC-12 Transmit Cycle Time†
OC-12 Output Time‡
OC-12 Receive Cycle Time
OC-12 Setup Time
OC-12 Hold Time
* _{Input from PHY}
† _{Output from C-5e NP}
‡ _{Aligned to TCLK, negative edge}
MIN TYP
12.86
40
12.86
-0.1
12.0 12.86
2.0
0.0
MAX UNIT
ns
60
%
ns
2.2 ns
ns
ns
ns
Cycle 3
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08