C5ENPB0-DS Datasheet, PDF (44/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

44
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 15 PCI Signals (continued)
SIGNAL NAME
PPAR
PIN #
AB1
PFRAMEX
W9
PTRDYX
AB9
PIRDYX
AB8
PSTOPX
AA5
PDEVSELX
AA4
PPERRX
AA3
PSERRX
AA1
PCLK
AA7
PRSTX
AA8
PREQX
AA9
PGNTX
Y7
PIDSEL
Y8
PINTA
Y9
TOTAL PINS
TOTAL TYPE I/O SIGNAL DESCRIPTION
1
PCI I/O Parity. This signal carries even parity for AD and CBE#
pins. It has the same receive and drive characteristics
as the address and data bus, except that it is one PCI
cycle later.
1
PCI I/O Cycle frame
1
PCI I/O Target ready for data transfer
1
PCI I/O Initiator ready for data transfer
1
PCI I/O Target transaction stop request
1
PCI I/O Target device selected
1
PCI I/O Bus parity error
1
PCI I/O System error
1
LVTTL I_PD Bus clock
1
PCI I Bus reset
1
PCI O Initiator bus request (arbitration)
1
LVTTL I_PD Initiator bus grant (arbitration)
1
PCI I Initialization device select
1
PCI O Interrupt (active low)
50
C5ENPB0-DS REV 08
Serial Interface Signals
The Serial interface is a bidirectional two-wire serial bus. It can use one of the following
formats:
• An 8bit data format followed by an acknowledge bit, which supports transfers at up to
400kbps (low speed).
• A 16bit IEEE 802.3 MDIO data format with 10bits of addressing, which supports
transfers up to 25MHz (high speed).
The signals and pins are identical for both the high and low speed protocols.
FREESCALE SEMICONDUCTOR