C5ENPB0-DS Datasheet, PDF (38/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

38
CHAPTER 2: SIGNAL DESCRIPTIONS
Figure 4 GMII/TBI Transmit and Receive Pin Configurations
Single Cluster Mode
Pin Configuration
Cluster
0
Tx
} _Rx
Port 1
Two Cluster Mode
Pin Configuration
Cluster
0
Cluster
1
Tx
} _Rx
Port 2
Cluster
1
Cluster
2
Tx
} _Rx
Port 3
Cluster
2
Cluster
3
Tx
} _Rx
Port 4
Cluster
3
nc = not connected
Tx
Rx
nc
Tx
} ^{Port 1}
nc
Rx
Tx
Rx
nc
Tx
} ^{Port 2}
nc
Rx
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example
SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL
CPn_0
Table 7 1
LVTTL O_PD T_CLK
CPn_1
Table 7 1
LVTTL I_PU TCLKI
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL O_PD TXD(0)
LVTTL O_PU TXD(1)
LVTTL O_PD TXD(2)
LVTTL O_PU TXD(3)
LVTTL O_PU TX_EN
CPn+1_0
CPn+1_1
Table 7 1
Table 7 1
nc
nc_PD nc
LVTTL I_PU COL
CPn+1_2
CPn+1_3
Table 7 1
Table 7 1
LVTTL O_PD TXD(4)
LVTTL O_PU TXD(5)
SIGNAL DESCRIPTION
GMII Transmit Clock (125MHz). This clock is used to synchronize the
transmit data.
MII transmit clock. Transmit data aligned to this clock input from
phy in MII mode. 25 Mhz in 100BaseT, 2.5 in Mhz in 10BaseT
Transmit Data (byte-wide data, least significant bit)
Transmit Data
Transmit Data
Transmit Data
Transmit Enable. When asserted, the data on TXD is encoded and
transmitted on the twisted pair cable.
nc
Collision. Asserted when both RX_DV and TX_EN are valid during
half duplex operation.
Transmit Data
Transmit Data
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR