C5ENPB0-DS Datasheet, PDF (39/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
39
Table 11 Gigabit Ethernet (GMII/MII) Signals One Cluster Example (continued)
SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL
SIGNAL DESCRIPTION
CPn+1_4
CPn+1_5
CPn+1_6
Table 7 1
Table 7 1
Table 7 1
LVTTL O_PD TXD(6)
LVTTL O_PU TXD(7)
LVTTL O_PU TX_ER
Transmit Data
Transmit Data (byte-wide receive data, most significant bit)
Transmit Error. Asserting TX_ER when TX_EN is a 1 causes
transmission of the designated “bad code” in lieu of the normal
encoded data on the twisted pair data.
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc_PD nc
I_PU RCLK
I_PD RXD(0)
I_PU RXD(1)
I_PD RXD(2)
I_PU RXD(3)
I_PU RX_DV
nc
Receive Clock (125MHz)
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Receive Data Valid. Indicates that there is a receive frame in progress
and that the data present on the RXD signals is valid.
CPn+3_0
CPn+3_1
Table 7 1
Table 7 1
nc
nc_PD nc
LVTTL I_PU CRS
nc
Carrier Sense. Indicates traffic is on the link. CRS is asserted when a
non-idle condition is detected on the receive data stream. CRS is
deasserted when an end of frame or idle condition is detected.
CPn+3_2
CPn+3_3
CPn+3_4
CPn+3_5
CPn+3_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL I_PD
LVTTL I_PU
LVTTL I_PD
LVTTL I_PU
LVTTL I_PU
RXD(4)
RXD(5)
RXD(6)
RXD(7)
RX_ER
Receive Data
Receive Data
Receive Data
Receive Data (most significant bit)
Receive Error Detected. Indicates that there has been an error
received in the receive frame.
TOTAL PINS
28
* _{n can be 0, 4, 8, or 12.}
† _{Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.}
Gigabit Ethernet and Fibre Channel TBI Configuration
1000BASE-T Gigabit Ethernet and Fibre Channel TBI is implemented in much the same
way as Gigabit Ethernet (GMII). Table 10 shows the possible CP pin combinations you can
use and Figure 4 shows receive and transmit pin configurations by cluster. Table 12 shows
the signals and pinouts for a single cluster for Gigabit Ethernet and Fibre Channel TBI.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08