C5ENPB0-DS Datasheet, PDF (100/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

100 CHAPTER 3: ELECTRICAL SPECIFICATIONS
* _{Not fully tested, values based on design/characterization.}
† _{Measured 0.8V to 2.0V.}
Table 54 Signal Groups in BMU Timing Diagrams
SIGNAL GROUP
Control (M_ctl)
Address (MAn)
Data (MDn)
INCLUDED SIGNALS
MBA0, MBA1, MCASX, MRASX, MWEX, MCSX, MDQM, MDQML
MA0 - MA11
MD0 - MD129, MDECC0 - MDECC8
TLU Timing Specifications The TLU timing specifications are shown in Figure 25 and described in Table 55.
Figure 25 TLU Timing Diagram
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
TCLKI
T_ctl
TAn
TDn
(output)
T_tdo
TDn
(input)
T_tc
T_tco
T_tao
T_tdz
T_tdv
Table 55 TLU Timing Description
SYMBOL
Ttc
Ttco
Ttao
Ttds
Ttdh
PARAMETER
TLU Cycle Time
TLU Ctrl Output
TLU Addr Output
TLU Data Setup
TLU Data Hold
MIN TYP
7.5
0.8
0.8
1.0
1.2
T_tds T_tdh
MAX UNIT
ns
4.0 ns
3.9 ns
ns
ns
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR