C5ENPB0-DS Datasheet, PDF (36/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

36
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 7 CP Physical Interface Signals and Pins (Grouped by Clusters) (continued)
CP CLUSTER 1
SIGNAL PIN #
CP3_5 AH25
CP3_6 AG25
CP CLUSTER 2
SIGNAL PIN #
CP7_5 AE21
CP7_6 AD21
CP CLUSTER 3
SIGNAL PIN #
CPB_5 AA21
CPB_6 Y29
CP CLUSTER 4
SIGNAL PIN #
CPF_5 U26
CPF_6 U25
DS1/T1 Framer Interface Configuration
Table 8 describes the serial framer interface signals. For each CP (0-15), you can
implement one serial Framer interface.
Table 8 DS1/T1 Framer Interface Signals
SIGNAL NAME*
CPn_0
CPn_1
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
TOTAL PINS
PIN #†
Table 7
Table 7
Table 7
Table 7
Table 7
Table 7
Table 7
TOTAL
1
1
1
1
1
1
1
7
TYPE
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
I/O LABEL
O_PD TCLK
I_PU RCLK
O_PD TData
O_PU TFrame
I_PD RData
I_PU RFrame
nc_PU nc
SIGNAL DESCRIPTION
Transmit Clock (1.544MHz)
Receive Clock (1.544MHz)
Transmit Data
Transmit Frame Synchronization
Receive Data
Receive Frame Synchronization
nc
* _{n can be from 0 to 15. See Table 7.}
† _{Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.}
10/100 Ethernet (RMII) Configuration
Table 9 describes the 10/100BASE-T Ethernet Reduced Media Independent Interface
(RMII) signals. For each CP (0-15), you can implement one 10/100 Ethernet interface.
Table 9 10/100 Ethernet Signals
SIGNAL NAME* PIN # TOTAL TYPE I/O LABEL
SIGNAL DESCRIPTION
CPn_0
CPn_1
Table 7 1
Table 7 1
LVTTL O_PD REF_CLK Transmit and Receive Clock (50MHz)
LVTTL I_PU
CRS_DV
Carrier Sense (CRS)/ Receive Data Valid (RX_DV). CRS indicates that
traffic is on the link, and is asserted if the signal is a 1 or an
alternating 1010... RX_DV indicates that a receive frame is in
progress and the data present on the RXD pins is valid. It is
asserted if this signal is a 1 for more than one cycle.
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR