C5ENPB0-DS Datasheet, PDF (42/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

42
CHAPTER 2: SIGNAL DESCRIPTIONS
Table 14 OC-12 Signals Example
SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL
CPn_0
Table 7 1
LVTTL O_PD TCLK
CPn_1
Table 7 1
LVTTL I_PU TCLKI
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
CPn+1_0
CPn+1_1
CPn+1_2
CPn+1_3
CPn+1_4
CPn+1_5
CPn+1_6
CPn+2_0
CPn+2_1
CPn+2_2
CPn+2_3
CPn+2_4
CPn+2_5
CPn+2_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
nc
nc
LVTTL
LVTTL
LVTTL
LVTTL
nc
nc
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
O_PD TXD(0)
O_PU TXD(1)
O_PD TXD(2)
O_PU TXD(3)
O_PU OOF
nc_PD nc
nc_PU nc
O_PD TXD(4)
O_PU TXD(5)
O_PD TXD(6)
O_PU TXD(7)
nc_PU nc
nc_PD nc
I_PU RCLK
I_PD RXD(0)
I_PU RXD(1)
I_PD RXD(2)
I_PU RXD(3)
I_PU FP
CPn+3_0
CPn+3_1
CPn+3_2
CPn+3_3
CPn+3_4
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
nc
nc
LVTTL
LVTTL
LVTTL
nc_PD nc
nc_PU nc
I_PD RXD(4)
I_PU RXD(5)
I_PD RXD(6)
SIGNAL DESCRIPTION
Deskewed Transmit Clock (77.76MHz). This clock is used to
synchronize the transmit data.
Transceiver Transmit Clock. This clock sets the frequency of the
transmit data and is typically sourced by the PHY chip.
Transmit Data (byte-wide data, least significant bit)
Transmit Data
Transmit Data
Transmit Data
Out of Frame
nc
nc
Transmit Data
Transmit Data
Transmit Data
Transmit Data (byte-wide data, most significant bit)
nc
nc
Receive Clock (77.76MHz)
Receive Data (byte-wide receive data, least significant bit)
Receive Data
Receive Data
Receive Data
Frame Synchronization Pulse. This is valid during the third A2 of
the receive SONET frame.
nc
nc
Receive Data
Receive Data
Receive Data
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR