C5ENPB0-DS Datasheet, PDF (27/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Table Lookup Unit
Table Lookup Unit
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Some of these parameters are programmed into the SDRAMs’ mode register and can be
applied only once per power cycle. The ECC functionality can be enabled or disabled via
configuration register writes.
If needed, the interface can narrowed to 128bits by disabling ECC and providing board
pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the
board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU
supports SDRAM devices that use 12 address lines. Internal address calculation paths limit
the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.
The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used
for statistics accumulation and retrieval and as general data storage. The TLU
simultaneously supports multiple application-defined tables and multiple search
strategies, such as those needed for routing, circuit switching, and QoS lookup tasks.
The C-5e NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules
(at frequencies up to 133MHz) for storage of its tables. These modules allow
implementation of tables with 2²⁵ x 64bit entries using 8Mbit SRAM technology. The
maximum amount of memory supported by the TLU is 128MBytes in four banks, when
SRAM technology supports 4M x 18pins parts.
Table 5 TLU SRAM Configurations
SRAM TECHNOLOGY
1Mbit (32k x 32pins)
2Mbit (64k x 32pins)
4Mbit (256k x 18pins)
8Mbit (512k x 18pins)
16Mbit (1M x 18pins)
32Mbit (2M x 18pins)
64Mbit (4M x 18pins)
MIN TABLE SIZE
(ONE BANK)
256kBytes
512kBytes
2MBytes
4MBytes
8MBytes
16MBytes
32MBytes
MAXIMUM TABLE SIZE
(FOUR BANKS)
1MBytes
2MBytes
8MBytes
16MBytes
32MBytes
64MBytes
128MBytes
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08