C5ENPB0-DS Datasheet, PDF (102/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

102 CHAPTER 3: ELECTRICAL SPECIFICATIONS
QMU SRAM (Internal The QMU SRAM (Internal Mode) timing specifications are shown in Figure 26 and
Mode) Timing described in Table 57.
Specifications
Cycle 1
Figure 26 QMU SRAM (Internal Mode) Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
QACLKI
Q_ctl
QAn
QDn
(output)
T_qdo
QDn
(input)
T_qc
T_qco
T_qao
T_qdz
T_qdv
T_qds T_qdh
Table 57 QMU SRAM (Internal Mode) Timing Description
SYMBOL PARAMETER
Tqc QMU Cycle Time
Tqco
Tqao
Tqds
Tqdh
Tqdo
QMU Ctrl Output
QMU Addr Output
QMU Data Setup
QMU Data Hold
QMU Data Output
MIN TYP MAX UNIT COMMENT
6.25
ns With QMU on-board memory
6.67
With QMU memory daughter board
0.8
3.9 ns Loading is 50Ω transmission line.
0.8
3.7 ns Loading is 50Ω transmission line.
0.8
ns
0.8
ns
0.9
4.0 ns Loading is 50Ω transmission line.
C5ENPB0-DS REV 08
FREESCALE SEMICONDUCTOR