C5ENPB0-DS Datasheet, PDF (89/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

AC Timing Specifications
89
CPn_2
Cycle 1
CPn_3
CPn_0
CPn_1
CPn_4
CPn_5
Cycle 1
T_c3r
T_c3d
OC-3 Timing Specifications
The OC-3 interface timing is shown in Figure 17 and described in Table 46.
Figure 17 OC-3 Timing Diagram
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_c3t
T_c3i
Cycle 2
Cycle 3
Cycle 4
Cycle 5
T_c3s T_c3h
T_c3s T_c3h
Table 46 OC-3 Timing Description
SYMBOL PARAMETER
MIN TYP
Tc3t
OC-3 Transmit Cycle Time
6.43
Tc3i
OC-3 Pulse Width
2.0
Tc3r
OC-3 Receive Cycle Time* 6.0
Tc3d OC-3 Clock Duty Cycle 40
Tc3s
OC-3 Setup Time
2.0
Tc3h OC-3 Hold Time
0.0
MAX UNIT
ns
ns
ns
60
%
ns
ns
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08