C5ENPB0-DS Datasheet, PDF (41/118 Pages) Freescale Semiconductor, Inc – C-5e Network Processor Silicon Revision B0

Pin Descriptions Grouped by Function
41
Table 12 Gigabit Ethernet and Fibre Channel TBI Signals Example (continued)
SIGNAL NAME* PIN #† TOTAL TYPE
I/O LABEL
SIGNAL DESCRIPTION
TOTAL PINS
28
* _{n can be 0, 4, 8, or 12}
† _{Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.}
SONET OC-3 Transceiver Interface Configuration
Table 13 describes the SONET Optical Carrier (OC) 3 transceiver interface signals. For each
CP (0-15), you can implement a single OC-3 interface.
Table 13 OC-3 Signals
SIGNAL NAME* PIN #† TOTAL TYPE I/O LABEL
SIGNAL DESCRIPTION
CPn_0
CPn_1
CPn_2
CPn_3
CPn_4
CPn_5
CPn_6
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
Table 7 1
LVPECL I_PD
LVPECL I_PU
LVPECL O_PD
LVPECL O_PU
LVPECL I_PD
LVPECL I_PU
LVPECL I_PU
RCLK_H
RCLK_L
TXD_H
TXD_L
RXD_H
RXD_L
SIGNAL_DET
Receive Clock noninverted side of pair (155.52MHz)
Receive Clock inverted side of pair (155.52MHz)
Transmit Data noninverted side of pair
Transmit Data inverted side of pair
Receive Data noninverted side of pair
Receive Data inverted side of pair
A light level above a certain threshold is present at the optical
receiver - single ended LVPECL.
TOTAL PINS
7
* _{n can be from 0 to 15.}
† _{Reference Table 7 for pin numbers for the actual cluster(s) you are configuring.}
SONET OC-12 Transceiver Interface Configuration
SONET Optical Carrier (OC) 12 is implemented by using one cluster of CPs. At any time, a
CP within a cluster spends half its time performing receive functions, and the other half
performing transmit functions. Table 14 shows a CP Cluster configured for one OC-12
interface.
FREESCALE SEMICONDUCTOR
C5ENPB0-DS REV 08